Download Integrated Circuit Design and Technology by M. J. Morant (auth.) PDF

By M. J. Morant (auth.)

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N+ doping for sources and drains of n-channel MOSTs. p+ doping for sources and drains of p-channel MOSTs, Contact holes to silicon and polysilicon, Meta! I patterning. Vias. Meta! 2 patterning, and Bond-pad windows in overglaze. Write a Iist of the steps needed to fabricate the bipolar transistor shown in Fig. 13 with its collector connected to a resistor. Include double-meta! connections. 1 Mask Requirements for ICs A complete IC fabrication process usually has 10-12 photolithography stages. Each stage uses a separate mask and the complete set of masks defines the shapes and the positions of all the doping windows, contacts and vias, and the patterning of the deposited polysilicon and meta!

It is useful to consider the cost pe r gate in deciding on the best Ievel of integration to use. Assuming that the chip area is always filled with gates at a certain density per square millimetre. arge numbers of the smallest possible chips to build a system at thc minimum cost! However this ignores the considerable cost of packaging thc chips and mounting them on PCBs. When these are included thc total assembled cost per gate has a minimum value at a certain chip area. Other things being equal.

8oth n-wcll and p-well processes are widely used and the choice between them depends on thc type of circuit tobe employed, as we shall see in Chapter 4. The cross-section of a pair of transistors formcd by a typical n-well CMOS process is shown in Fig. 8. There are many variations on this type of structure produced by different manufacturers. One alternative that can improve the electrical performance is to use both p- and n-type wells in a near-intrinsic epitaxial layer although, with more fabrication stages, this is a moreexpensive technology.

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