By S. A. Knight

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Example text

For every value assigned to RL in a particular circuit there will be a corres­ ponding (and different) load line. If Vcc is maintained constant, all the possible lines will start at the same point (Q) but will cut the IQ axis at different points P. Increasing RL will reduce the gradient of the line and vice-versa. Quite clearly the collector voltage can never exceed VQQ (point Q) and equally the collector current can never be greater than that value which would make VQE zero (point P). Using the circuit example of Fig 2 we have ^CE = VQQ = 12 V, when / c = 0 /c = ^cc RL = 12 A = 12 mA, when VQE = 0 1000 51 6 The load line is drawn on the characteristics shown in Fig 8 which we assume are the characteristics for the transistor used in the circuit of Fig 2 earlier.

9 V] o +25 Vf- W- • -12 VH Fig 16 2 The square wave shown in Fig 16 is applied to the rectifier system shown. v. applied to the diode; (b) the current flowing in the 1 k& load resistor. [(a)32V;(b)5mA] 31 Ί Fig 17 (above, left) 1 Γ 100 -|200 -GOO Fig 18 (above, right) -MOO H500 Fig 19 (right) -UoO f /JmA) 3 A sinusoidal voltage represented by v = 100 sin 200 irt volts is applied to a circuit made up of an ideal diode in series with a 50 Ω resistor. s. value of the supply voltage; (b) the average value of the rectified voltage; (c) the ripple frequency?

1 mA. 2 mA and back again to 0 mA during the course of each input cycle. Hence the operating point moves up and down the load line in phase with the input current and hence the input voltage. A sinusoidal input cycle is shown on Fig 8. The output signal voltage O ce ) and current (/c) can be obtained by projecting vertically from the load line on to FCE and IQ axes respectively. When the input current i\> varies sinusoidally as shown, then vce varies sinusoidally if the points A and B at the extremities of the input excursions are equally spaced on either side ofX.