By JosA© T. de Sousa, Peter Y.K. Cheung
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Extra info for Boundary-Scan Interconnect Diagnosis (Frontiers in Electronic Testing)
Inside the IC, the BSCs are connected in series, so that a shift register known as the Boundary-Scan Register (BSR) is formed. In this way, the test data can circulate through all signal pins of the IC, solely using the ICs TDI and TDO serial I/Os. A BSC associated with an input pin can monitor the logic level present at the respective external net, or drive the respective input of the internal core logic. A BSC associated with an output pin can monitor the respective output of the internal core logic or drive the respective external net.
The former allows interpreting any suspect nets that produce the same response as being shorted. The latter is utilized to identify any suspect nets as potentially open. The S-A-0/1 fault model is also used as an analytic model to diagnose shorts to ground or power nets. This page intentionally left blank 3 BEHAVIORAL INTERCONNECT DIAGNOSIS Diagnosis of interconnect faults comprises synthesis of test vectors and analysis of responses. In this chapter an original study of behavioral schemes for diagnosis of interconnect faults is presented.
SMT chips can be highly complex and miniaturized, and come in small packages with very low pitches. Such low spacings between the IC pins make it difficult and expensive to miniaturize bed-of-nails fixtures accordingly. For technologies that enable direct mounting of silicon dies on both sides of the board, such as tape automated bonding (TAB) or chip on board (COB), this problem becomes even worse. 6 Boundary-scan testing ICT is rapidly becoming obsolete, and a substitute technology has become a major priority.