Download Analog Circuit Design: Smart Data Converters, Filters on by Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund PDF

By Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund

Analog Circuit layout includes the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and invaluable layout rules within the quarter of analog circuit layout. each one half is gifted by way of six specialists in that box and cutting-edge details is shared and overviewed. This e-book is quantity 18 during this profitable sequence of Analog Circuit layout, supplying beneficial details and ideal overviews of: clever info Converters: Chaired through Prof. Arthur van Roermund, Eindhoven college of expertise, Filters on Chip: Chaired via Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired through Prof. M. Steyaert, Catholic college Leuven, Analog Circuit layout is a necessary reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the academic insurance additionally makes it appropriate to be used in a complicated layout.

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2 m CMOS. IEEE J. Solid-State Circuits 31(3), 294–303 (1996) 18. Y. , A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. IEEE J. SolidState Circuits 39(12), 2139–2151 (2004) 19. K. Bult, Embedded analog-to-digital converters, in Proceedings of the ESSCIRC, Athens, 2009, pp. 52–64 20. S. Kawahito, Low-power design of pipeline A/D converters, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2006, pp. 505–512 21. -C. Huang, T,-C. 5 mW pipelined ADC with a time sharing technique, in ISSCC Digest of Technical Papers, San Francisco, CA, USA, Feb 2010, pp.

A disadvantage of this technique is that, because of the fact that the common mode voltage at the input of the comparator lowers during the successive SAR cycles as shown in Fig. 4b, the signal-dependent comparator offset can cause a degradation in ADC linearity. 4 Discussion It is interesting to note that a lot of recent SAR improvements have focused on this reduction of capacitor switching energy. While in fact, it is often not the most power consuming block in the ADC. The implementation in [5] uses only 20% of the total power budget for this.

T. , Power dissipation bounds for high-speed Nyquist analog-to-digital converters. IEEE Trans. Circuits Syst. I 56(3), 509–518 (2009) Chapter 3 Low-Power Successive Approximation ADCS for Wireless Applications Jan Craninckx Abstract This chapter discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8–10 bit and a few 10’s of MHz sampling speed. An overview is given of recent techniques that reduce the switching power in the capacitive DAC, and as such improve the power efficiency of the ADC up to levels that are out of reach of the typically used pipeline architecture.

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